André Seznec Receives Eckert–Mauchly Award

Even if microprocessors have embraced multicore architectures featuring tens, sometimes hundred of cores on the same die, sequential performance of a single core is still an issue. One of the difficulties is that the processor should normally wait for the full execution of an instruction before even knowing what will be the next. To avoid this difficulty, processors implement a so-called branch predictor which function is to guess the outcome of an instruction before its actual execution. The processor starts the execution of predicted instruction without waiting for the effective execution of the previous one, thus saving precious execution cycles when the prediction happens to be correct.

In 2006, André Seznec proposed a new branch predictor called TAGE which the industry has broadly accepted. “Today, you find it in all the PCs, tablets, servers, as well as most of the telephones.” The Eckert-Mauchly Award comes as a recognition of this pioneering contribution to computer architecture.

State-of-the-Art Branch Predictor

In a nutshell, multiple tagged branch history tables are indexed with different path lengths. “You hope to obtain the right prediction from a table with the shortest history length possible; And TAGE is designed precisely to do that: predict the right path from the shortest history length.”

André Seznec is also renowned for a cache mapping technique that he introduced back in 1993 under the name ‘skewed associative cache’. In essence, a piece of information can be stored indifferently in various places in the cache. But conflicts often occur during the retrieval of this data and precious time is being lost in the process. Using hash functions, Seznec’s method enables to swiftly reduce the cache miss rate, thus improving the execution performance of applications.

Mentored by the late Jacques Lenfant, an expert in the design of very high-speed processors who later became president of Rennes 1 University, André Seznec has been with the Inria research institute, in Rennes, since 1983, first as PhD student, then as a researcher. Later he successively headed two project-teams (CAPS and ALF) for a period spanning from 1994 to 2016.

An IEEE Fellow since 2013, an ACM fellow since 2016, he was awarded an Intel Research Impact Medal in 2012 and an Intel Outstanding Research Award in 2019. He was also the recipient of the 2020 IEEE B. Ramakrishna Rau Award and the 2022 Inria – Académie des Sciences – Dassault Systèmes Innovation Prize.

In 2010, the European Research Council (ERC) awarded him an Advanced Grant for Defying Amdahl’s Law, a project meant to enhance the performance of multicore processors’ sequential sections. “This help was really awesome. As a ERC grantee, one is provided with the financial means to focus only on research as well as to recruit PhD students and postdoctoral researchers to see this work through.”

Close Contact with the Industry

In 1999, Seznec spent one year with Compaq. “It turned out to be a very valuable experience because I got to see that my work was relevant. It's very important for academic researchers, at least in my discipline, to be in touch with the industry and validate that what they are doing makes sense in relation to industry's problems. Being confronted with the industry also allows to discover, even sometimes anticipate issues that will become important in the next decades.”

Two decades later, Seznec still applies the precept to himself. From 2021 to 2024, he thus went to work for Intel’s Advanced Architecture Development Group. And no sooner was he back at Inria, that the phone rang again. He has now joined  SiFive, a company whose chip implements the RISC-V instruction set architecture. “As a scientist, this is a beautiful adventure because we start from a blank page!”