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Emmanuelle Perrot - 23/04/2012

Olivier Temam, recognized for his Franco-Chinese collaboration.

Olivier Temam, responsable de l'action exploratoire ByMoore

Olivier Temam, Senior Research Scientist at Inria and leader of the ByMoore exploratory action, has been recognized twice (in 2010 and 2011) as part of the Chinese Academy of Sciences’ “International Talents Program”, for his cooperation with ICT (Institute of Computing Technology) in Beijing. And in February, his former PhD student, Zheng Li, himself received an award for research excellence for his PhD thesis. This prize is awarded by the Chinese government to Chinese students who have obtained their theses abroad, and there are about 500 recipients among the tens of thousands of Chinese PhD students (in all scientific disciplines) graduating abroad every year. Olivier Temam has recently established a joint team with ICT (YOUHUA) within the framework of the Franco-Chinese Lab for Computer Science, Automation and Applied Mathematics (LIAMA) after first setting up an INRIA associate team. Olivier talks us about the rationale and benefits of this collaboration.

Could you remind us of Moore’s law and the challenges researchers face in pushing its boundaries?

Moore’s law (by Gordon Moore, co-founder of Intel) is actually a prediction stating that the size of transistors can be halved approximately every 18 to 24 months. This reduction in the size of transistors offers two benefits: an increase in the number of transistors per unit of surface area and an increase in the (switching) speed of transistors. These two properties are, to a large extent, the reason for the performance increase of computers over the past 40 years.
This increase has also been considered to be one of the main drivers of economic growth for the last twenty years or so. However, since 2004, the sector has experienced a number of technology shocks, which have seriously called into question our ability to continue to improve the performance of processor architectures. First of all, constraints associated with power consumption and the dissipation of heat have greatly restricted the increase of processor speed (clock speed), forcing us to turn to multi-core architectures, where the improvement in performance stems from parallelism. Nevertheless, because of new, and ever more stringent, power constraints, even the multi-core option is now being challenged. This will force us to design heterogeneous multi-core architectures, i.e., combinations of cores and accelerators. Accelerators are specialized circuits which can each execute only a limited set of algorithms, unlike cores, but they can be far more efficient, energy-wise, than cores. In the future, there is a strong possibility that a lot of the computing heavy lifting will be done by such  accelerators, for both general-purpose and embedded systems.

What are the key research issues you are working on with ICT ?

Initially, we attempted to answer the following question: while it is already difficult for the majority of programmers to create applications for multi-core architectures, what kind of environment could be designed to facilitate the programming of heterogeneous multi-core architectures, which are even more complex? The key point is that the non-expert end-user should not be exposed to the complexity of such architectures, while still being able to take advantage of their potential performance. We are working on a programming environment capable of reconciling these seemingly contradictory goals for accelerator-based architectures.

At the same time, we also attempted to answer the following question: what kind of accelerators should we be designing? The main difficulty is to resolve the tension between the custom nature of accelerators and their utilization in  architectures meant to tackle a broad range of applications. For this reason, we are developing a special form of reconfigurable architectures, more energy efficient and easier to program than current FPGAs thanks to their coarse granularity and their specific control circuit. This work is conducted in partnership with ICT, as well as the École Polytechnique Fédérale de Lausanne (EPFL) and the joint NTU (Singapore)-Rice (US) laboratory.

 Why choose China as a partner for these topics?

Inria usually tries to partner with the leading academic and industrial players of each domain. In the domain of architectures and compilation, Inria’s teams work with many American and European universities as well as with large industrial groups (Intel, ARM and STMicroelectronics, etc.). ICT is not only China’s most advanced academic institution in the field of architecture and compilation, but it has also founded the company Loongson Technologies, which many consider as a future major player in the domain of computing architectures. The position of ICT/Loongson as an emerging academic and industrial player makes them more open to both external partnerships and new approaches (such as the introduction of accelerators) than more established organizations. Therefore, there is a real opportunity, right now, to establish a special relationship with what will certainly become a major player in the domain over the coming years.

Keywords: INRIA Saclay - Île-de-France Moore's law Olivier Temam Internationale ByMoore